Google Partners with AMD on Next-Gen TPU Featuring On-Package CPU Cores

Google is reportedly collaborating with AMD to develop a new version of its Tensor Processing Unit (TPU) as part of the upcoming 10th-generation family. The partnership, highlighted in a SemiAnalysis note, suggests that AMD’s expertise in CPU IP, advanced packaging and system-in-package (SiP) technology could be leveraged to create a hybrid AI ASIC that integrates general-purpose cores directly onto the TPU die. The move appears to be driven by a growing demand for reinforcement-learning (RL) and other agentic AI workloads that require more CPU-heavy processing alongside traditional tensor operations. While large language model training remains dominated by accelerator-centric designs, RL workloads often need a tighter coupling of general-purpose compute and tensor engines to achieve efficient reasoning and decision-making. ## Why AMD Might Join the Project Google has already built nine generations of its proprietary TPUs, with Broadcom handling silicon design and Google providing the accelerator architecture. The analysts argue that Google does not need AMD to design a conventional TPU for inference (V10i) or training (V10t). Instead, the value proposition lies in AMD’s CPU IP and packaging capabilities. AMD’s data-center-grade Instinct MI300A, which combines x86 cores with accelerator chiplets, demonstrates the company’s ability to produce tightly integrated heterogeneous packages. If the speculation holds, the new TPU could feature Google-designed tensor compute chiplets paired with AMD-supplied CPU cores and high-bandwidth memory (HBM) within a single package. Such a design would shrink the distance between the CPU and accelerator, potentially lowering latency, improving power efficiency, and simplifying system-level integration for RL tasks. ## Shifts in Google’s TPU Architecture Recent TPU generations already show a trend toward higher CPU density. The TPU 8i, aimed at inference, reasoning and RL, pairs one Google Axion CPU with every two TPUs, a notable increase from the earlier 7th-generation setup that used one Xeon “Emerald Rapid” processor per four TPUs. Some internal reports even suggest a 1:1 CPU-to-accelerator ratio may be optimal for certain workloads, indicating that future AI hardware could become considerably more CPU-centric than current designs. Embedding CPU cores directly into the TPU package would be a logical next step in this evolution, reducing interconnect overhead and enabling tighter coordination between general-purpose and tensor compute. While Intel is another potential partner-given its existing collaborations with Google-it lacks experience in building hybrid x86-plus-accelerator data-center chips, making AMD a more plausible candidate for this specific role. ## What This Means for the AI Hardware Landscape If the collaboration proceeds as described, the key takeaway is not merely that AMD is assisting Google with another TPU iteration, but that Google is exploring a new class of TPU optimized for RL and agentic AI. By incorporating on-package CPU cores, the design could address the unique compute patterns of reinforcement learning, where traditional accelerator-only solutions may fall short. The report remains speculative, and details about the exact nature of AMD’s involvement are still unclear. Nonetheless, the potential introduction of a CPU-heavy TPU variant could signal a broader shift in AI hardware strategy, where heterogeneous integration becomes a cornerstone for tackling increasingly diverse workloads. --- *This article is based on analysis from SemiAnalysis and reporting by Tom’s Hardware. All statements about future hardware capabilities are attributed to the sources and have not been independently verified.*