Intel Details Xeon 7 'Diamond Rapids' Package Design at HOT CHIPS
Intel has detailed the package design of its next-generation Xeon 7 "Diamond Rapids" server processor. The processor is designed to be a versatile serial processing powerhouse for enterprise-scale agentic AI.
The Xeon 7 "Diamond Rapids" processor is built on a disaggregation philosophy similar to AMD EPYC, with CPU cores being spun out in small groups of CPU core complexes (CCXs) contained in CPU core dies (CCDs), groups of which interface with a centralized server I/O die (sIOD), which serves as a system agent and I/O hub.
The "Diamond Rapids" MCM consists of two Fabric Hub Tiles (FHTs), four CPU core Base Tiles, and a total of 16 core chiplets, each containing 16 "Panther Cove" P-cores. The core-count per compute base tile is 64, and four of these add up to 256 cores.
| Component | Details |
|---|---|
| Fabric Hub Tiles | 2, built on Intel 3 foundry node |
| CPU core Base Tiles | 4, built on Intel 3-T foundry node |
| Core Chiplets | 16, each containing 16 "Panther Cove" P-cores, built on Intel 18A-P foundry node |
Intel is employing Foveros 3D Direct hybrid bonding interface to interconnect the four core chiplet tiles on the compute base tiles. The base tile provides high density microscopic wiring that interconnects the four tiles on top, and aggregates their wiring to the Fabric Hub Tiles.
The base tile is more than just a glorified interposer for the four core chiplets on top, there's a reason the company chose a fairly advanced foundry node such as Intel 3-T for this tile, when most traditional interposers can make do with older, more mature nodes.
The core chiplets only contain CPU cores with their dedicated L2 caches, but don't feature shared L3 caches. They instead feature a 3D crossbar (Xbar) which facilitates transfers among the 16 P-cores contained in the core chiplets, and connects them to the base tile.
It is the base tile that contains a last-level cache (LLC) that's shared among the four core chiplets. This way, Intel has been able to achieve LLC pooling among 64 cores. Each base tile features a massive 320 MB L3 cache shared among the four core chiplets.
Intel built the Fabric Hub tile on the Intel 3 foundry node. There are two of these, each connects to four compute base tiles. The Fabric Hub Tiles contain the processor's memory controllers.
| Fabric Hub Tile | Details |
|---|---|
| Number | 2 |
| Foundry Node | Intel 3 |
| DDR5 Memory Interface | 8-channel |
| PCI-Express Gen 6 Lanes | 64, configurable as CXL 3.0 lanes, and UPI 3 |
| PCI-Express Gen 4 Lanes | 8, for low-level platform connectivity |
Each of the two Fabric Hubs puts out 64 PCI-Express Gen 6 lanes, which are configurable as CXL 3.0 lanes, and UPI 3. They also feature eight PCIe Gen 4 lanes for low-level platform connectivity. Intel has also given each of the two Fabric Hubs a full set of fixed-function accelerators, including TDX, SGX, QAT, and DSA.
Not much is known about the "Panther Cove" P-cores, but the ISA details put out in this presentation talk about support for Advanced Matrix Extensions (AMX), AVX 10.2, and support for data formats such as FP8, FP16, and BF16.
