Synopsys Achieves Breakthrough in 3D Stacked PCIe 6.0 PHY
Synopsys has successfully validated a PCIe 6.0 PHY inside a face-to-face 3D stack at 64 GT/s, paving the way for faster and more efficient data transfer in future hardware
Synopsys has announced a major breakthrough in the development of 3D stacked PCIe 6.0 PHYs, achieving a data transfer rate of 64 GT/s per lane and up to 128 GB/s across an eight-lane link using PAM4 signaling. This milestone was reached by modifying an existing 2D test chip and incorporating through-silicon vias (TSVs) to enable face-to-face hybrid bonding.
## Background on 3D Stacking In traditional monolithic chips, PCIe PHYs are located at the perimeter of the die, close to the package I/O connections, to minimize signal attenuation and reflections. However, in 3D stacked packages, this layout is not feasible, and signals must be routed through TSVs to reach the substrate. This requires careful design and planning to avoid signal corruption and ensure reliable data transfer.
## Challenges in 3D Stacking According to Manmeet Walia, executive director of product management at Synopsys, 3D stacking poses significant challenges, including electromigration and layout rules that change substantially compared to 2D designs. Additionally, the via count must be carefully managed to balance bandwidth and signal integrity. Walia also noted that customer logic sitting over the PHY's path down to the substrate can be a challenge that requires iterative design and refinement.
## Comparison with Other Approaches In contrast to Synopsys' approach, Fujitsu's Monaka processor uses a different strategy, stacking four N2 compute chiplets face-to-face on N5 SRAM chiplets using hybrid copper bonding, and placing the memory controllers and PHYs on a separate I/O die. The following table compares the key features of these two approaches: | Feature | Synopsys 3D Stacked PCIe 6.0 PHY | Fujitsu Monaka Processor | | --- | --- | --- | | Stacking Technology | Face-to-face hybrid bonding | Hybrid copper bonding | | PHY Location | Inside the stacked package | On a separate I/O die | | Data Transfer Rate | Up to 128 GB/s | Not specified |
## Future Developments Looking ahead, Walia predicted that 3.5D packaging will become increasingly important, with PCIe PHYs being replaced by UCIe and relocated to a side chiplet on the interposer. This will enable a multi-protocol hub for Ethernet, PCIe, and CXL, and further increase data transfer rates. While no specific timeline has been announced, Synopsys' blog noted that leading-edge customers are already evaluating angstrom-class process technologies for the top dies in their stacks.
