Samsung zHBM Merges Memory and Compute
Samsung has detailed a three-stage HBM roadmap ending with zHBM, a 3D architecture stacking DRAM directly on processors to tackle AI data bottlenecks.
Samsung has revealed a three-stage roadmap for High Bandwidth Memory, culminating in a radical architecture called zHBM. The plan, presented at Hot Chips 2026, aims to vertically stack DRAM directly on top of processors, fundamentally merging memory and compute.
Samsung is shifting its HBM development focus. The company is no longer solely pursuing higher DRAM stacks and faster transfer rates. Instead, it plans to make the base die of the HBM stack increasingly intelligent. This will eventually move significant processing functions into the memory system itself.
The Evolution to an Intelligent Base Die
Current HBM architecture stacks DRAM dies vertically above a base die. This entire stack is then placed beside a GPU or AI accelerator on an interposer. Starting with HBM4, Samsung is fabricating the base die on an advanced 4nm logic process, not the DRAM-oriented technology used for the memory layers. This improves power efficiency and reduces die area. Crucially, it provides a piece of advanced logic silicon underneath every HBM stack.
The roadmap exploits this logic layer progressively. The first phase adds more sophisticated control functions to the HBM base die while keeping conventional processing on the main processor. Later generations can offload additional operations into that logic layer. This reduces the volume of data that must travel back and forth to the primary accelerator.
The Ultimate zHBM Configuration
The final zHBM configuration eliminates the conventional horizontal separation between compute and memory. Instead of placing HBM stacks beside the processor, Samsung's concept stacks DRAM vertically over the XPU. This creates a three-dimensional memory-and-compute structure. According to the source, this could address one of AI hardware's largest bottlenecks: moving data.
Samsung states contemporary HBM4 stacks offer roughly 1 to 5 TB/s of bandwidth. Scaling this performance further with more I/O connections and higher frequencies makes package design difficult and power-hungry. Reducing the physical distance between compute and memory could improve bandwidth, energy efficiency, and latency all at once.
Significant Technical and Market Hurdles
The primary challenge is thermal management. A modern AI processor can dissipate hundreds or even thousands of watts. Stacking heat-sensitive DRAM immediately above such silicon creates an extremely difficult cooling problem. Yield, serviceability, and manufacturing costs will also become substantially more complex.
For PC gaming hardware, zHBM is not an upcoming technology. GDDR will remain far more economical for conventional graphics cards for the foreseeable future. However, developments in advanced packaging often migrate over time. Technologies developed today for massive AI accelerators could influence future chiplet CPUs, integrated GPUs, and high-performance APUs.
Samsung has announced no commercial launch date for zHBM. The company is showing a direction, not a finished product. That direction is significant. future memory may stop behaving as passive storage and become part of the processor itself.
