Samsung Targets Doubled HBM5 Performance
Samsung aims to double performance and improve power efficiency by 20% with its next-generation HBM5 memory, potentially using a 4,096-bit interface.
Samsung has set aggressive performance targets for its upcoming HBM5 memory. The goal is to double bandwidth and improve performance per watt by 20% compared to the current HBM4E generation.
Choi Jang-seok, head of the product planning team for Samsung's memory business, announced the targets at the Memory Executive Summit ahead of Semicon Taiwan 2026. The company had previously stated that its HBM5 stacks will incorporate a heat path block to reduce thermal resistance by 20%.
Projected Bandwidth and AI Applications
Doubling the per-stack bandwidth of HBM5 could lead to peak speeds of around 4 terabytes per second per stack by 2028 or 2029. Foundry partner TSMC expects future AI accelerator packages to incorporate 20 to 24 HBM5 or HBM5E stacks by the end of the decade. Such a configuration would deliver a massive 80 to 96 terabytes per second of total memory bandwidth for these systems-in-package.
The Engineering Challenge
To achieve its stated goal, the HBM5 specification would require significant changes. The official JEDEC data transfer rate for HBM4E is expected to be around 12 gigatransfers per second. Current HBM4 and HBM4E controllers from various suppliers are already rated for 16 GT/s.
| Specification | HBM4E (Reference) | Potential HBM5 Requirement |
|---|---|---|
| Target Bandwidth vs. HBM4E | - | 2x (Double) |
| Performance per Watt Improvement | - | 20% |
| Data Transfer Rate (GT/s) | ~12 GT/s | Up to 24 GT/s |
| Interface Width (bits) | 2,048 | Up to 4,096 |
Doubling HBM5's bandwidth relative to HBM4E would necessitate either doubling the per-pin data rate to 24 GT/s, doubling the interface width from 2,048 to 4,096 bits, or a combination of both. Researchers from KAIST and Marvell have previously envisioned a 4,096-bit interface.
The Path to Efficiency
From an energy efficiency perspective, widening the interface is generally considered easier than doubling the per-pin signaling speed. Higher transfer rates demand faster components and more sophisticated physical interfaces to maintain signal integrity. However, a 4,096-bit interface introduces its own complexities, requiring twice the number of interconnects and a more complicated base die. A Tom's Hardware analysis suggests a 3,072-bit interface paired with a moderate speed increase could be a viable engineering compromise, though JEDEC's final decision remains unknown.
The report notes that the projected 20% gain in energy efficiency could come from several areas beyond raw performance increases. Improvements in DRAM process technology, base die optimization, lower interconnect voltages, architectural changes, or enhanced power management could all contribute.
Any discussion of the final HBM5 specification is currently speculative. Samsung's target to double the bandwidth of HBM4E within a single generation is described as very aggressive. The company's tease provides a clear direction for future high-bandwidth memory development aimed at next-generation computing workloads.
